1. Field of the Invention
The present invention relates to a chemical-mechanical polishing (CMP) process. More particularly, the present invention relates to a chemical-mechanical polishing proximity correction method and correction pattern thereof for reducing shadowing effects.
2. Description of the Related Art
Many types of processes are used in the fabrication of semiconductor devices. However, photolithographic process is one of the most important because that is what the critical dimension (CD) and hence overall level of integration of the finished product depends. To increase the critical dimension in photolithography, a few methods for increasing the resolution of photomask such as optical proximity correction (OPC) and phase shift mask (PSM) has been developed.
The optical proximity correction is a method that attempts to eliminate the deviation of critical dimension due to proximity effect. Proximity effect is most prominent for a fabrication process with a small line width. An optical proximity correction method is applied to resolve proximity effect in the active area and the outer corners in U.S. Pat. No. 6,451,680, for example.
The aforementioned proximity effect also occurs when a chemical-mechanical polishing (CMP) operation is performed to polish a wafer in the fabrication of integrated circuit. In general, the problem is most significant in the corner region of a polish area.
FIG. 1 is a top view showing a conventional method of defining a wafer into a protected area and a polish area before performing a chemical-mechanical polishing operation. FIG. 2 is a cross-sectional view along line II—II of FIG. 1. As shown in FIGS. 1 and 2, a wafer 100 with device structures 200 therein is provided. The wafer 100 is divided into a polish area 102 and a protected area 104. Before carrying out a chemical-mechanical polishing operation, a material layer 202 is formed over the wafer 100 so that a portion of the material layer 202 within the polish area 102 is subsequently removed. To protect the device structures 200 outside the polish area 102, a protective layer is formed over the material layer 202 and then the protective layer within the polish area 102 is removed so that a protective layer 204 remains over the protected area 104.
In general, the upper surface of the protective layer 204 within the protected area 104 and the upper surface of the stop layer (the device structures 200) within the polish area 102 may not be at the same horizontal level. Typically, the protective layer 204 is at a slightly higher level. This causes the so-called shadowing effect at the boundary between the polish area 102 and the protected area 104. In other words, the material below the dash line in FIG. 2 (a boundary strip just outside the protected area 104) is very difficult to remove.
One solution to the shadowing effect is shown in FIG. 3. FIG. 3 is a schematic cross-sectional view showing another conventional method of defining a wafer into a protected area and a polish area before performing a chemical-mechanical polishing operation. As shown in FIG. 3, the wafer 300 is divided into a polish area 302 and a protected area 304. Furthermore, device structures 301 and 303 are formed in the polish area 302 and the protected area 304 of the wafer 300 respectively. The stop layer within the polish area 302 (the upper section of the device structure 301) is raised to match the top surface of the protective layer 308 within the protected area 304. Since the top of the device structure 301 is at a higher or the same level as the top surface of the protective layer 308, shadowing effect is eliminated after the material layer 306 is removed in a chemical-mechanical polishing operation. However, this method demands a major modification of the device structures inside a wafer and hence unsuitable for fabricating most semiconductor devices.